CUI Aijiao
Address:
HITSGS Campus,Shenzhen University Town,Xili, Shenzhen, China (518055)
Email:
cuiaj@hit.edu.cn
Phone:
PERSONAL PROFILE
 
RESEARCH INTEREST
 
1. Digital watermarking techniques for VLSI IP protection
2. Design-for-Testability of VLSI
3. Logic synthesisi and Optimization for VLSI

The students with interest of IC design and IC test are welcome to join our research.
EDUCATION  
205-2009
Ph.D. in Electronics Engineering,Nanyang Technological University
Thesis:Constraint-based watermarking techniques for VLSI IP protection
2000-2003
Master of Engineering in Electronics Engineering, Beijing Normal University
Thesis:Research on NTP-based Timing system
1996-2003
Bachelor of Engineering in Communication System, Beijing Normal University
Thesis:Research on Timing system based on GPS and Radio
RESEARCH & WORK EXPERIENCE  
2010-
assistant professor, Master student supervisor, School of Electronic and Information Engineering, Harbin Institute of Technology Shenzhen Graduate School
2003-2004
teaching assistant,School of Electronic and Information Engineering, Beijing Jiaotong University
2009-201-
research staff, Shenzhen SoC Key Laborary of Peking University
PROFESSIONAL QUALIFICATION & ACADEMIC SERVICE
 
2006-
IEEE member
2011-
appointed reviewer for IEEE Transactions on VLSI, Integration, the VLSI Journal and Microelectronics Journal
2012-
reviewer for National Natural Science Foundation of China, Natural Science Foundation of Zhejiang Province
RESEARCH PROJECTS
2011-2013
Project supported by the National Science Foundation for Young Scholars of China :Research of Field Detectable Hybrid Dynamic Watermarking Technique for VLSI IP Protection (Grant No. 61006019)
2009-2010
Project supported by Shenzhen Basic Science Research Foundation:The application of watermarking technique in VLSI IP protection(Grant No. JC200903180629A)
2012-2014
Project supported by Shenzhen Basic Science Research Foundation:Research of Scan tree based DfT technique for VLSI(Grant No. JCYJ20120613140025732)
2012-2013
Project supported by Innovation Foundation of Harbin Institute of Technology:Research of low overhead IP watermarking technique based on DfT (Grant No. JA29100001)
2013-2015
Project supported by Innovation Foundation of Harbin Institute of Technology:Research of Dynamic IP watermarking technique for application on IP service platform
RESEARCH ACHIEVEMENT & AWARDS
PATENT
   
PAPER & BOOK PUBLICATIONS
[1] Aijiao Cui, C. H. Chang and S. Tahar, “A robust FSM watermarking scheme for IP protection of sequential circuit design,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,vol. 30, no. 5, May 2011, pp. 678-690.(SCI,IF=1.258)
[2] C. H. Chang and Aijiao Cui, “Synthesis-for-Testability watermarking for field authentication of VLSI intellectual property,” IEEE Trans. on Circuits and Systems I, vol. 57, no. 7, August 2010,pp. 1618-1630..(SCI,IF=1.580)
[3] Aijiao Cui, C. H. Chang and S. Tahar, “IP watermarking using incremental technology mapping at logic synthesis level,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 9, Sept. 2008, pp. 1565-1570..(SCI,IF=1.466)
[4] Yongxia, Liu, Aijiao Cui,"An efficient zero-aliasing space compactor based on elementary gates" on proceedings of 2013 13th International Conference on Computer-Aided Design and Computer Graphics, accepted(EI index).
CONFERENCE PAPERS/TALKS
 
[1] Yongxia, Liu, Aijiao Cui,"An efficient zero-aliasing space compactor based on elementary gates" on proceedings of 2013 13th International Conference on Computer-Aided Design and Computer Graphics, Nov. 2013, pp. 95-100.
[2] L. Chen and Aijiao Cui, “A power-efficient scan tree design by exploring the Q-D connection,” in Proceedings IEEE International Symposium on Circuits and Systems, Beijing, China, May 2013, pp. 1018-1021.
[3] Aijiao Cui, and C. H. Chang, “A Post-processing scan-chain watermarking scheme for VLSI intellectual property protection” in Proceedings IEEE Asia Pacific Conference on Circuits and Systems, Kaohsiung, Taiwan, pp. 412-415, Dec. 2012.
[4] Aijiao Cui, C. H. Chang and L. Zhang, “A hybrid watermarking scheme for sequential functions,” in Proceedings IEEE International Symposium on Circuits and Systems, Rio. Brazil, pp. 2333-2336, May 2011.
[5] Aijiao Cui and C. H. Chang, “An improved publicly detectable watermarking scheme
based on scan chain ordering,” Proc. IEEE Int. Symp. on Circuits and Syst., Taipei, May 2009, pp. 29-32.
[6] Aijiao Cui and C. H. Chang, “Intellectual property authentication by watermarking scan chain in design-for-testability flow,” Proc. IEEE Int. Symp. on Circuits and Syst., Seattle, USA, May 2008, pp. 2645-2648.
[7] Aijiao Cui and C. H. Chang, “Watermarking for IP Protection through Template Substitution at Logic Synthesis Level,” Proc. IEEE Int. Symp. on Circuits and Syst., New Orleans, USA, May 2007, pp. 3687-3690.
[8] Aijiao Cui and C. H. Chang, “Kernel Extraction for Watermarking Combinational Logic Networks,” Proceedings IEEE Asia Pacific Conference on Circuits and Systems, Singapore, December 2006, pp. 1023-1026.
[9] Aijiao Cui and C. H. Chang, “Stego-signature at logic synthesis level for digital design IP protection,” Proceedings IEEE International Symposium on circuits and Systems, Kos, Greece, May 2006, pp. 4611-4614.
TEACHING/SUPERVISING EXPERIENCE
School of Electronic and Information Engineering, HIT Shenzhen Graduate School
Updated:2018-09