WANG Mingjiang
Address:
Xili University Town, Nanshan District, Shenzhen City, Harbin Institute of Technology Campus, Room C (518055)
Email:
mjwang@hit.edu.cn
Phone:
86-755-26033791
86-755-26033791(Fax)
PERSONAL PROFILE
 
Mainly engaged in low-power voice signal processing, voice processing low-power chip, artificial intelligence cognitive technology, artificial intelligence processor, long-term recruit Ph.D student, postdoctoral; the main research directions:
(1) Artificial intelligence processing technology for speech and video, artificial intelligence processor technology;
(2) Voice processing technology, low-power voice processing chip;
Ph.D tutor according to the actual work results, to give project subsidies. Welcome Interested students to apply.
RESEARCH INTEREST
 
The main research directions are as follows:
(1) Artificial intelligence processing technology, artificial intelligence processing chip research; The main research includes image/speech depth learning algorithm, image/speech depth learning algorithm VLSI implementation, cognitive and intelligent formation mechanism;
(2) Voice processing technology, low-power voice chip design. The main research includes voice front-end noise reduction technology, low-power voice processing technology;
(3) Embedded applications; including FPGA, ARM platform, embedded LINUX, ANDROID technology, embedded application development;
(4) High-performance ADC, DAC technology research;
(5) Industrial control IC. Mainly study of motor digital control technology and ASIC implementation;
EDUCATION  
1995.9~1998.7
Ph.D., CAD,Department of Electronic Engineering, Fudan University, Shanghai, China
1990.9~1993.3
Master, semiconductor physics and semiconductor device physics, Harbin Institute of Technology, Harbin, China
1986.9~1990.7
Bachelor, Semiconductor Physics and Semiconductor Devices Physics, Harbin Institute of Technology, Harbin, China
RESEARCH & WORK EXPERIENCE  
2009.8~now
Professor, School of Electronics and Information Engineering, Harbin Institute of Technology (Shenzhen),Shenzhen, China
2003.9~2009.7
Associate Professor, School of Electronics and Information Engineering, Harbin Institute of Technology, Shenzhen Graduate School,Shenzhen, China
2000.12~2003.8
Senior Engineer, Jingmen Technology (Shenzhen) Technology Co., Ltd, Shenzhen, China
1998.8~2000.7
Senior engineer, Shenzhen Huawei Technologies Co., Ltd. Shenzhen, China
1995.9~1998.7
Assistant Professor, National Integrated Circuit System Engineering Technology Research Center, Southeast University, Nanjing, China
PROFESSIONAL QUALIFICATION & ACADEMIC SERVICE
 
RESEARCH PROJECTS
2014
Research on the Enhancement Technique of Audio
2014
All-digital hearing aid SoC (system-on-chip) chip key technology research and development
2015
Guangdong Province integrated circuit design EDA technology innovation support platform
2015
Active de-noising voice processing algorithm software development
2016
Multi-Stage Vibration Coupling Project Based on Micro-Mechanical System
2017
Research on Key Technologies of Audiovisual Perception and Human-Computer Interaction for Service Robot
RESEARCH ACHIEVEMENT & AWARDS
PATENT
   
1. Dotted line combination of fingerprint identification method, ZL200810064819.9
2. A fast and efficient fingerprint refinement method, ZL200810137353.0
3. A full-duplex asynchronous serial communication method, ZL201310574696.4
4. Video coding motion estimation unit hardware circuit, ZL201400537198.7
5. A speech vector recognition vector quantization rapid convergence method, ZL201410281283.1
6. A method of improving speech robustness based on speech inter-frame dynamic information, ZL201410281239.0
7. A suitable for hardware implementation of HEVC motion estimation method, ZL201410392865.7
PAPER & BOOK PUBLICATIONS
1.Variable Tap-Length NLMS Algorithm with Adaptive Parameter ,IEICE T FUND ELECTR,2017 VLSI implementation of the modified sign-error LMS adaptive algorithm [J]. (SCI)
2.Liu De, Wang Mingjiang. Delay-optimized floating point fused add-subtract unit [J]. IEICE Electronics Express, 2015, 12(17): 1-10. (SCI)
3.Liu De, Wang Mingjiang. A two-item floating point fused dot-product unit with latency reduced [J]. IEICE Electronics Express, 2016, 13(23): 1-12. (SCI)
4.Ming Liu, Mingjiang Wang, De Liu. VLSI implementation of the modified sign-error LMS adaptive algorithm [J]. IEICE Electronics Express, 2016, (SCI)
5.Ming Liu, Mingjiang Wang, De Liu. Delay-optimized realization of 2-parallel delayed LMS adaptive FIR filter[J]. IEICE Electronics Express, 2017,( SCI)
6.Boya Zhaoa, Mingjiang Wang, and Ming Liu. An Energy-Efficient Coarse Grained Spatial Architecture for Convolutional Neural Networks AlexNet[J]. IEICE Electronics Express, 2017,( SCI)
7.Weihao Zeng, Ming Liu, Mingjiang Wang. Hearing Environment Recognition in Hearing Aids[C]//Fuzzy Systems and Knowledge Discovery (FSKD) (SCI)
8. "Design and implementation of a kind of walking-assisted lower extremity exoskeleton", Xie Zheng, Wang Mingjiang, Huang Wulong, Yong Shanshan, Wang Xinan, Peking University (Natural Science Edition) doi: 10.13209 / j.0479-8023.2017.056 ( EI)
9.“An efficient VLSI computation reduction scheme in H.264/avc motion estimation”,Zuo Shikai,Wang Mingjiang,Xiao Liyi,WSEAS Transactions on Signal Processing, v 10, n 1, p 178-187, 2014. (EI)
10. “A simulation platform for reconfigurable processor”, Dai, Peng; Wang, Mingjiang; Wang, Xin'an,Journal of Computational Information Systems, v 9, n 4, p 1659-1668, February 15, 2013. (EI)
11. “Implementation of High-Definition Video Coding on Reconfigurable Processor ”, Dai Peng, Wang Mingjiang, Wang Xin'an, Microelectronics, Vol43(1), p60-4, Feb. 2013. (EI)
12. “Variable Tap-Length NLMS Algorithm with Adaptive Parameter”, Yufei Han, Mingjiang Wang, Boya Zhao, IEICE T FUND ELECTR, 2017,(SCI)
CONFERENCE PAPERS/TALKS
 
A Matress System for Human Biosignals Monitoring, Ming-Jiang Wang, Peng Dai,2012 Prognostics & System Health Management Conferenc,2012;
Design and Realization of Multi-mode Screensaver Based on μC/OS-II Embedden System, Jia-Ying Xue, Ming-Jiang Wang*,International Conference on Granular Computing,2012;
A new hardware architecture for H.264 intra prediction frame processing, Shou-Gen Xu,Ming-Jiang Wang*,IMSAA,2011 IEEE 5th International Conference on Digital Object Identifier, 2011;
A cache hardware design for h.264 encoder, Shi-Kai Zuo, Mingjiang Wang*, IMCCC 2012;
Design and Implementation of PROFIBUS-DP Intelligent Slave Station Controlle, Peng-Fei Yu, Mingjiang Wang* , IMCCC 2012;
TEACHING/SUPERVISING EXPERIENCE
Master program:
Embedded processor architecture and system design, 32 hours, 2 ciredits
Ph.D program:
On chip Network design, 32 hours, 2 ciredits
Master tutor:
2003~now
Ph.D tutor:
2009~now
Updated:2017-10